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High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells

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3 Author(s)
M. Ferretti ; Dept. of Eletrical Eng. Syst., Southern California Univ., Los Angeles, CA, USA ; R. O. Ozdag ; P. A. Beerel

This work presents a back-end design flow for high performance asynchronous ASICs using single-track full-buffer (STFB) standard cells and industry standard CAD tools to perform schematic capture, simulation, layout, placement and routing. This flow is demonstrated and evaluated on a 64-bit asynchronous prefix adder and its test circuitry. The STFB standard cells provide low latency and fast cycle-times at the expense of some timing assumptions. This paper demonstrates that, by controlling top-block sizes and/or wire length within the place & route flow, ultra-high-performance circuits can be automatically designed. In particular, in the TSMC 0.25μm process our post-layout STFB standard-cell 64-bit asynchronous prefix adder requires 0.96 mm2, offers a latency of 2.1 ns, has a throughput of 1.4 GHz, and operates at five process corners as well as a wide-range of temperatures and voltages.

Published in:

Asynchronous Circuits and Systems, 2004. Proceedings. 10th International Symposium on

Date of Conference:

19-23 April 2004