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Test vector minimization during logic synthesis

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2 Author(s)
Ku, T.-W. ; Data Gen. Corp., Sunnyvale, CA, USA ; Chia, W.-K.

A novel approach is presented to minimize the 100% single-stuck (SS) fault test vector set of a synthesized circuit during the logic synthesis process. In the synthesis process for any given two-level primary and irredundant (PI) network, the authors first define a specific SS fault test vector set of the two-level network and prove that it is a superset of the 100% SS fault test vector set for the synthesized circuit. Instead of generating all the vectors in this superset, they develop an algorithm to minimize this superset during the logic optimization and technology mapping process. Then, they generate the test vectors by using a two-level test generator. The experimental data demonstrates that the resultant number of test vectors can be up to 40% less than that of the conventional method such as PODEM in many cases, while the additional CPU time used for test vector generation is about 5% of the conventional method on average.<>

Published in:

Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on

Date of Conference:

11-15 Nov. 1990