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An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator

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4 Author(s)
Kong-pang Pun ; Dept. of Electron. Eng., Chinese Univ. of Hong Kong, China ; Chiu-sing Choy ; Cheong-Fat Chan ; J. E. da Franca

This paper presents a technique to suppress the mismatch between the in-phase (I) and quadrature-phase (Q) channels of a switched-capacitor complex sigma-delta modulator that is used for the analog-to-digital conversion of a real intermediate-frequency radio signal. The mismatch is suppressed through time sharing of the critical capacitors, i.e., the input sampling capacitor and the capacitor of the feedback digital-to-analog converter, between the I and Q channels. Circuit simulations verifying the proposed technique are presented.

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IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:51 ,  Issue: 5 )