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Optimization of the parallel technique for compiled unit-delay simulation

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1 Author(s)
Maurer, P.M. ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA

The parallel technique is a purely compiled method for unit-delay simulation that is based on levelized compiled simulation and bit parallel simulation. The parallel technique provides rapid simulations with a reasonable amount of code, but there are opportunities for optimization. The author presents two schemes: bit-field trimming and shift-elimination. Performance results are presented that demonstrate an average performance improvement of 47%.<>

Published in:

Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on

Date of Conference:

11-15 Nov. 1990

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