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Automatic and semi-automatic verification of switch-level circuits with temporal logic and binary decision diagrams

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3 Author(s)
Fujita, M. ; Fujitsu Lab. Ltd., Kawasaki, Japan ; Matsunaga, Y. ; Kakuda, T.

Automatic and semi-automatic verification methods for switch-level circuits are presented. Switch-level circuits with no delay (but with/without charge effects) are automatically verified using a formalism with binary decision diagrams (BDD) and temporal logic. Purely bidirectional transistors, such as those whose signal directions are dynamically determined in operations, are treated in the uniform way as nonbidirectional transistors. In the case of switch-level circuits with arbitrary delays, based on the work by M.E. Leeser (1989), the authors present a semi-automatic verification method which uses a propositional theorem prover using BDD. First some assignments of propositional variables to terms of temporal logic are manually given, and then the automatic theorem prover does verification.<>

Published in:

Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on

Date of Conference:

11-15 Nov. 1990