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We present an intellectual property (IP) core of the entire advanced encryption standard (AES) algorithm. Our design utilizes the T-box algorithm to implement the Rijndael round function. By analyzing the pipelining dataflow, a new architecture, which combines the multiplexing and the iteration architecture, is also proposed. The designs are implemented using the integrated systems engineering (ISE) 5.1i software on a single Virtex-E XCV812E field programmable gate array (FPGA) device. As a result, the AES IP core operates at 61MHz with the key scheduler resulting in a throughput of l.9Gbps for the AES encryption and decryption with the block size of 128 bits and the flexible key size. A comparison is provided between our design and similar existing implementations.