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Leakage power reduction using self-bias transistor in VLSI circuits [digital circuits]

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2 Author(s)
Gopalakrishnan, H. ; Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA ; Wen-Tsong Shiue

Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold currents. Minimizing leakage, by power gating logic circuits using sleep transistors gives considerable power savings. However, this technique cannot be used in sequential circuits and memory cells, as it would result in loss of stored data. In this paper, we propose a novel circuit by applying a self-bias transistor (SBT) to minimize sub-threshold leakage currents in static and dynamic circuits. This circuit with SBTs, acts as a smart switch by virtually power gating either pull-up or pull-down logic, and causes a considerable reduction in leakage currents in both active and standby modes. A benchmark is simulated with 0.18 μm CMOS technology in the Cadence Spectre circuit simulator. Results show significant reduction in leakage power, of up to 50% on average, for all possible states simulated in static and dynamic circuits by applying this proposed self-bias transistor.

Published in:

Microelectronics and Electron Devices, 2004 IEEE Workshop on

Date of Conference:

2004