By Topic

TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Seong-Dong Kim ; IBM Microelectron., Essex Junction, VT, USA ; Wada, H. ; Woo, J.C.S.

The effects of line edge roughness (LER) of nanometer scale gate pattern on the MOS transistor parameter fluctuations and their technology scaling are investigated using the simplified modeling and statistical analysis based on two-dimensional technology CAD (TCAD) tools. From the simple statistical analysis, it is shown that the gate patterns without appropriate LER may cause severe device parameter and performance fluctuations in highly scaled nanometer technologies, resulting in a negative average threshold voltages shift, a subthreshold slope degradation, an unrealistic effective channel length extraction and an exponential increase in off-state leakage current due to LER-induced inhomogeneous channel potential. The characteristics of the average off-state leakage current and the threshold voltage uncertainty as a function of technology scaling provide a useful guideline for advanced gate patterning process and demand much tighter control of LER less than 3-5 nm for a successful CMOS scaling into deep nanometer scale physical gate length regime below 50 nm.

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:17 ,  Issue: 2 )