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A previously proposed parallel and scalable hybrid data/command driven architecture (HDCA) was dynamic/reconfigurable at defined "application" and "node" levels only and was to be implemented with multiple chips. The HDCA is now being developed and experimentally verified as a versatile high performance fault tolerant single-chip multiprocessor computer system-on-chip (SoC) that can execute a wide range of real-time and/or non-real-time signal processing and other applications. It is now being developed to be dynamic/reconfigurable at three levels: the "application", "node", and "processor architecture" levels. A three-phase final prototype development process is being utilized for a complete HDCA SoC. Each phase includes addition and validation of functionality to allow the architecture to be fully dynamic/reconfigurable, in sequence, at the application, node, and processor architecture levels. Experimental hardware prototype testing results are shown for a first-phase prototype of the HDCA. Experimental hardware prototype testing results illustrate that the single-chip first-phase HDCA prototype is able to achieve its functional goal of being able to correctly execute, in a parallel manner, applications described by process flow graphs of different topologies using a heterogeneous mix of processors.