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Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

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15 Author(s)
Shiyang Zhu ; Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore ; Yu, H.Y. ; Whang, S.J. ; Chen, J.H.
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This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-κ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of Ion/Ioff∼107-108 and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D , Ion/Ioff can reach ∼105 at Vds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-κ dielectric and metal-gate materials to be used in the future generation CMOS technology.

Published in:

Electron Device Letters, IEEE  (Volume:25 ,  Issue: 5 )

Date of Publication:

May 2004

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