Referenced Items are not available for this document.
The possibility of implementing the double-sampling (DS) techinque in infinite impulse response (IIR) first- and second-order switched-capacitor (SC) decimators is considered. The DS-SC circuits that result are designed using the same procedure as standard IIR decimators, and only a different SC implementation results with a reorganized clock phasing. The main advantage is that the time allowed for the op-amps to settle can be equal to the output sampling period rather than one half of it. Using the proposed DS decimators allows the design of high-frequency SC filtering systems (an antialiasing SC decimator filter and a `core' DS-SC filter) where the op-amp speed requirements are the same in each block
Published in:
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
(Volume:39
,
Issue:
4
)
Date of Publication: Apr 1992
- Page(s):
- 300 - 304
- ISSN :
- 1057-7122
- INSPEC Accession Number:
- 4172999
- Digital Object Identifier :
- 10.1109/81.129459
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Apr 1992
- Sponsored by :
- IEEE Circuits and Systems Society
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