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A VLSI neural processor for image data compression using self-organization networks

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4 Author(s)
Wai-Chi Fang ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Sheu, B.J. ; Chen, O.T.-C. ; Joongho Choi

An adaptive electronic neural network processor has been developed for high-speed image compression based on a frequency-sensitive self-organization algorithm. The performance of this self-organization network and that of a conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results. The neural network processor includes a pipelined codebook generator and a paralleled vector quantizer, which obtains a time complexity O(1) for each quantization vector. A mixed-signal design technique with analog circuitry to perform neural computation and digital circuitry to process multiple-bit address information are used. A prototype chip for a 25-D adaptive vector quantizer of 64 code words was designed, fabricated, and tested. It occupies a silicon area of 4.6 mm×6.8 mm in a 2.0 μm scalable CMOS technology and provides a computing capability as high as 3.2 billion connections/s. The experimental results for the chip and the winner-take-all circuit test structure are presented

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Neural Networks, IEEE Transactions on  (Volume:3 ,  Issue: 3 )