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VLSI implementation of synaptic weighting and summing in pulse coded neural-type cells

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3 Author(s)
Gyu Moon ; Dept. of Electr. Eng. & Comput. Sci., George Washington Univ., DC, USA ; Zaghloul, M.E. ; Newcomb, R.W.

Presents the hardware realization for synaptic weighting and summing using pulse-coded neural-type cells (NTCs). The basic information processing element (NTC) encodes the information into the form of pulse duty cycles using voltage-controlled resistors, for which a pulse duty cycle modulation technique is proposed. Summation is executed by a simple capacitor circuit as a current integrator. Layouts and measurements on a fabricated integrated design are included

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Neural Networks, IEEE Transactions on  (Volume:3 ,  Issue: 3 )