Referenced Items are not available for this document.
A simple and fast algorithm for solving the two-terminal board level routing problem in FPGA-based logic emulation systems is presented. The method is based on the net scan selection process. Experimental results are the first implemented results for an algorithm presented previously. The comparison results show that the current approach achieves better effectiveness and uses less CPU time.
Published in:
Electronics Letters
(Volume:40
,
Issue:
8
)
Date of Publication: 15 April 2004
- Page(s):
- 469 - 470
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 8215403
- Digital Object Identifier :
- 10.1049/el:20040277
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 04 May 2004
- Issue Date :
- 15 April 2004
- Sponsored by :
- Institution of Engineering and Technology
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