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Concurrent error detection (CED) schemes utilising time redundancy can keep chip area and interconnect to a minimum. An efficient time redundancy scheme, RESO, for array dividers has been reported. Under the same cell fault model, an alternated time redundancy CED scheme using alternating logic (AL) approach is proposed. Two array dividers are considered: nonrestoring array divider (NRD) and restoring array divider (RSD). The key to the detection of faults using AL approach is determining that at least one input combination exists for which the error does not result in alternating outputs. Results of this study show that the proposed design achieves the same CED capability as RESO implementation with a lower area overhead. Owing to the simplicity, low area overhead, and the cell fault model, the proposed AL approach will be very attractive to the design of fault-tolerant VLSI-based system.