A VHDL library of LNS operators

Logarithmic number system (LNS) have been shown to be a competitive replacement of floating-point (FP) arithmetic, for precisions up to 32 bits. This paper presents a library of LNS operators aimed at smaller precisions typical of DSP applications. The novelty of our approach is the use of multipartite table compression in the addition and subtraction operators. The paper compares this approach to other published implementations, and to similar FP operators. The operators have been developed and tested on FPGAs, but they are written in fairly standard VHDL. They are available for download from www.ens-lyon.fr/LIP/Arenaire.