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Some results on Taylor-series function approximation on FPGA

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2 Author(s)
Lee, B. ; Univ. of Wales, Cardiff, UK ; Burgess, N.

This paper presents results from the design of a parameterised function approximation unit on FPGA. The Taylor-series expansion is used to approximate a function f(x) of 8 to 26-bits over a given domain [a, b]. A search of the 1st, 2nd and 3rd order Taylor expansions is performed for each operand length to find the most area efficient implementation in terms of LUT usage of a representative FPGA technology. Results show that trading lookup-logic and arithmetic-logic reduces the exponential logic requirement that occurs if a predominantly ROM based approximation is used.

Published in:

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on  (Volume:2 )

Date of Conference:

9-12 Nov. 2003