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Modeling and mitigation of jitter in high-speed source-synchronous interchip communication systems

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2 Author(s)
Ganesh Balamurugan ; Illinois Univ., Urbana, IL, USA ; Naresh Shanbhag

Jitter significantly limits the maximum achievable data rates (MADR) over high-speed source-synchronous I/O links. In this paper, we present a simple model that comprehends transmitter and receiver jitter in a source-synchronous I/O link. We show that the channel can have a significant impact on transmit jitter at high data rates, resulting in 1.1X-3.8X jitter amplification for typical cases. We quantify the performance degradation of transmit/receive equalization and multilevel modulation schemes, due to jitter in high-speed I/O links. We present two design techniques to mitigate the effect of jitter on performance-transmission of a slower source-synchronous clock, and jitter equalization. Both techniques can improve MADR by 13% when signaling over a 20" FR4 channel.

Published in:

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on  (Volume:2 )

Date of Conference:

9-12 Nov. 2003

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