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In this paper, we present energy-efficient soft error (SE)-tolerant techniques for digital signal processing (DSP) systems. The proposed technique, referred to as algorithmic soft error-tolerance (ASET), employs an low-complexity estimator of a main DSP block to guarantee reliability in presence of soft errors either in the MDSP or the estimator. For FIR filtering, it is shown that the proposed technique provides robustness to soft error rates of up to Per=10-2 in single-event upset (SEU). It is also shown that the proposed techniques provide 40%∼61% savings in power dissipation over that achieved via triple modula redundancy (TMR) when the desired signal-to-noise ratio SNRdes=25∼35 dB.