By Topic

System design of a low-power I/O link

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
S. R. Sridhara ; ECE Dept, Illinois Univ., Urbana, IL, USA ; Ganesh Balamurugan ; N. R. Shanbhag

In this paper, we present a detailed analysis of the system design choices available for low-power high-speed I/O link transceivers. Using the transceiver power dissipation as the metric, we compare three equalization schemes (linear equalizer, decision-feedback equalizer, and transmit pre-emphasis) in combination with three pulse amplitude modulation (PAM) schemes (2-PAM, 4-PAM, and 8-PAM). The input signal levels and the filter lengths in the equalizer are chosen to minimize the power dissipation while meeting a bit error rate constraint. We show that, for a typical 20" intersymbol interference dominated link, transmit pre-emphasis in combination with 4-PAM results in 75 data rates.

Published in:

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on  (Volume:2 )

Date of Conference:

9-12 Nov. 2003