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System design of a low-power I/O link

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3 Author(s)
Sridhara, S.R. ; ECE Dept, Illinois Univ., Urbana, IL, USA ; Ganesh Balamurugan ; Shanbhag, N.R.

In this paper, we present a detailed analysis of the system design choices available for low-power high-speed I/O link transceivers. Using the transceiver power dissipation as the metric, we compare three equalization schemes (linear equalizer, decision-feedback equalizer, and transmit pre-emphasis) in combination with three pulse amplitude modulation (PAM) schemes (2-PAM, 4-PAM, and 8-PAM). The input signal levels and the filter lengths in the equalizer are chosen to minimize the power dissipation while meeting a bit error rate constraint. We show that, for a typical 20" intersymbol interference dominated link, transmit pre-emphasis in combination with 4-PAM results in 75 data rates.

Published in:

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on  (Volume:2 )

Date of Conference:

9-12 Nov. 2003