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An efficient and scalable radix-4 modular multiplier design using recoding techniques

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2 Author(s)
Tenca, A.F. ; Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA ; Tawalbeh, L.A.

This paper presents the algorithm and architecture of a scalable radix-4 Montgomery multiplier. The straightforward implementation of a radix-4 design based on the techniques already published results in a poor solution. In this paper we present an algorithm and architecture for the scalable radix-4 multiplier that makes use of two types of digit receding in order to generate an efficient solution. The word-by-word algorithm used in the multiplier gives to the designer the freedom to select the level of parallelism according to the available area. Experimental results are shown to demonstrate that the proposed radix-4 Montgomery multiplier design has better area/performance tradeoff than previous radix-2 and 8 scalable designs.

Published in:

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on  (Volume:2 )

Date of Conference:

9-12 Nov. 2003