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Low-power aspects of different adder topologies

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4 Author(s)
M. Vratonjic ; Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA ; B. R. Zeydel ; H. Q. Dao ; V. G. Oklobdzija

This paper explores different adder topologies for low power solutions. Further, we look at the energy optimization of circuits using transistor sizing technique based on logical effort. The efficiency of the method is verified on representative 16-bit adders, commonly found blocks in general purpose DSP processors. The results are shown and analyzed in the energy-delay space.

Published in:

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on  (Volume:2 )

Date of Conference:

9-12 Nov. 2003