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Logarithmic number system and floating-point implementations of a well-conditioned RLS estimation algorithm on FPGA

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2 Author(s)
B. Lee ; Commun. Res. Centre, Univ. of Wales, Cardiff, UK ; K. Lever

This paper presents the results from the implementation of a recursive least squares estimation algorithm on FPGA and compares the implementation using two types of arithmetic. The estimation uses an orthogonal set of discrete Chebyshev polynomials to overcome the ill-conditioning problem that is exhibited by the classical least mean squared linear regression algorithm using the Taylor expansion. A recursive form of the algorithm is implemented at varying precision word lengths on FPGA using a recently developed set of logarithmic number system macros and a set of parametrised IEEE-754 compliant floating-point cores. Speed and area metrics are presented.

Published in:

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on  (Volume:1 )

Date of Conference:

9-12 Nov. 2003