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In this paper, architecture and circuit design of a beamforming baseband receiver IC for uplink W-CDMA communication systems is presented. In the proposed receiver, a four-antenna-element beamformer and a four-finger RAKE combiner are adopted to exploit both spatial diversity and path diversity receiving. To minimize the size and power consumption of the receiver, a latch-based 1024-tap complex delay line is custom designed for the matched filter in the channel estimation circuit. The receiver chip was fabricated in a 0.35-μm n-well CMOS single-poly quadruple-metal technology. The minimum supply voltage with the chip running at the nominal 15.36-MHz clock rate is measured at 2.15 V. The chip has an area of 6 mm by 6.3 mm and a power consumption of about 123 mW.