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In this brief, we investigate the potential of reduced swing clock networks for low-power applications. We designed and laid out a full swing conventional and a reduced swing H-tree clock distribution network in 0.13-/spl mu/m CMOS technology operating at 500 MHz. In the reduced swing clock network, the swing was reduced in the global clock distribution network and was restored to the full swing in the local clock distribution domains. The post-layout simulation results of this research shows that a power saving of 22% under nominal operating condition is feasible.