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Summary form only given. Designing a high performance microprocessor is extremely time-consuming taking at least several years. An important part of this design effort is architectural simulation which defines the microarchitecture or the organization of the microprocessor. The reason why these simulations are so time-consuming is fourfold: (i) the architectural design space is huge; (ii) the number of benchmarks the microarchitecture needs to be evaluated with, is large; (iii) the number of instructions that need to be simulated per benchmark is huge as well; and (iv) simulators are becoming relatively slower due to the increasingly complex designs of current high performance microprocessors. In this tutorial, we discuss these issues and propose a solution for each of them. As such, we present an architectural simulation framework for designing high performance microprocessors which reduces the total simulation time by several orders of magnitude without sacrificing accuracy. This is done by combining several recently proposed techniques, such as statistical simulation, representative workload design using statistical data analysis techniques, trace sampling and reduced input sets.
Date of Conference: 2004