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A high resolution, stictionless, CMOS compatible SOI accelerometer with a low noise, low power, 0.25 μm CMOS interface

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3 Author(s)
Amini, B.V. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Pourkamali, S. ; Ayazi, F.

The implementation and characterization of a high sensitivity silicon-on-insulator (SOI) capacitive microaccelerometer with sub-25 μg resolution is presented. The in-plane accelerometers were fabricated on 40 μm thick SOI substrates using a two-mask, dry-release low temperature process comprising of three plasma etching steps. The fabricated devices were interfaced with a high resolution, low noise and low power switched-capacitor integrated circuit (IC) fabricated in a 2.5 V 0.25 μm N-well CMOS process. The measured sensitivity is 0.2 pF/g and the output noise floor is 20 μg/√Hz. The total power consumption is 3 mW.

Published in:

Micro Electro Mechanical Systems, 2004. 17th IEEE International Conference on. (MEMS)

Date of Conference:

2004

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