By Topic

An architecture for WSI rapid prototyping

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Jain, V.K. ; Center for Miocroelectron. Res., Univ. of South Florida, Tampa, FL, USA ; Hikawa, H. ; Keezer, D.C.

Wafer-scale integration architecture for rapid prototyping (WARP), a generalized architecture for rapid prototyping, is discussed. The primary goal of rapid prototyping is to map one of several members of a class of algorithms using a single-wafer architecture. The wafer can be personalized for the algorithm by either soft or hard-restructuring. The WARP wafer consists of an array of two types of cells specifically defined for this architecture: the universal multiply-subtract-add (UMSA) cell and the universal nonlinear (UNL) cell. Reconfiguration of the algorithms in the presence of defects, a harvesting probability model and yield, and wafer-scale testing and test facilities are described.<>

Published in:

Computer  (Volume:25 ,  Issue: 4 )