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A design and yield evaluation technique for wafer-scale memory

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2 Author(s)
Yamashita, K. ; Fujitsu Labs. Ltd., Atsugi, Japan ; Ikehara, S.

Wafer-scale memory provides greater yet cheaper storage volume than conventional memory systems using discrete chips. A simulator using a Monte Carlo technique to evaluate the defect tolerance scheme for a wafer-scale memory and predict the harvested capacity of the wafer memory is described. The design of a wafer-scale random-access memory that uses switching-register network logic is presented. A simulator that selects the optimal defect tolerance scheme for the wafer-scale memory is discussed.<>

Published in:

Computer  (Volume:25 ,  Issue: 4 )