Skip to Main Content
Communicating real-time state machines (CRSM) are a formal modelling language for the development of distributed real-time systems. This paper proposes a mapping from CRSM to timed automata in the context of the Uppaal tool, with the purpose of enabling temporal validation and verification activities respectively based on simulation and model checking of a CRSM system. Usefulness and limitations of the mapping process are demonstrated through the verification of a real-time modelling example.
Industrial Technology, 2003 IEEE International Conference on (Volume:1 )
Date of Conference: 10-12 Dec. 2003