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Package to board interconnection shear strength (PBISS): effect of surface finish, PWB build-up layer and chip scale package structure

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4 Author(s)
Canumalla, S. ; R&D Center, Nokia Mobile Phones, Irving, TX, USA ; Hee-Dong Yang ; Viswanadham, P. ; Reinikainen, T.O.

The quality of the interconnection in a fine pitch, area array chip scale package (CSP) is evaluated at the system level using a new test method, the package to board interconnection shear strength (PBISS) technique. The influence of printed wiring board (PWB) sample finish, build-up layer and package structure are quantified after surface mount assembly. Clear differences were evident in the shear strength and fracture location data indicating that the PBISS method is sensitive to the presence of black pad, weak build-up layer and package stiffness. The PBISS value of the CSPs with OSP/RCC-FR4 pad/build-up layer combination were measured to be 37 ± 6 MPa and 38 ± 2 MPa for the two different structures investigated. The PBISS method is demonstrated to be a viable candidate technique to quantify interconnection quality at the system level due to issues such as black pad, etc. and this method can help identify weaknesses in the interconnection chain for effective assessment of supplier or product quality.

Published in:

Components and Packaging Technologies, IEEE Transactions on  (Volume:27 ,  Issue: 1 )