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SMART (strategic memory allocation for real-time) cache design using the MIPS R3000

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2 Author(s)
Kirk, D.B. ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; Strosnider, J.K.

SMART, a technique for providing predictable cache performance for real-time systems with priority-based preemptive scheduling, is presented. The technique is implemented in a R3000 cache design. The value density acceleration (VDA) cache allocation algorithm is also introduced, and shown to be suitable for run-time cache allocation

Published in:

Real-Time Systems Symposium, 1990. Proceedings., 11th

Date of Conference:

5-7 Dec 1990