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A novel hardware processor to compute elliptic curve scalar multiplication is proposed. It is based on a bit serial systolic architecture which performs both binary field division and multiplication by using a single type processing element. The field elements are represented in standard form. This scalable unidirectional bit serial systolic architecture can process finite fields of any dimension and any defining irreducible polynomial. It is optimized to have the least storage space while a clock rate over 700 MHz is achieved in the CMOS 0.18 μ technology using standard library cells.
Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004. International Conference on (Volume:2 )
Date of Conference: 5-7 April 2004