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We present a general algorithm to design fast parallel multipliers in any basis over GF(2m), avoiding any basis-dependent procedure or "ad hoc" optimization, as usually proposed in literature. Although the total number of gates is not guaranteed to be the absolute minimum, the algorithm is aimed at minimizing the number of XOR gates, reaching the minimum for the AND gate number. For the sake of comparison, lower and upper bounds to space and time complexities have been explicitly evaluated. As a significant example, for several in of practical interest, the algorithm has been applied to Gaussian normal basis parallel multipliers.
Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004. International Conference on (Volume:2 )
Date of Conference: 5-7 April 2004