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Architectural design features of a programmable high throughput AES coprocessor

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3 Author(s)
Hodjat, A. ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; Schaumont, P. ; Verbauwhede, I.

Programmable, high throughput domain specific crypto processors are required for different networking applications. We present the architectural design features that lead to a multiple Gbits/s rate AES coprocessor, which is programmable with domain specific instructions for Gbit throughput IPSec and other applications. Our design is a loosely coupled, independently working crypto-coprocessor that runs AES in ECB, CBC-MAC, Counter, and CCM modes of operation at a maximum throughput of 3.43 Gbits/s in a 0.18 μm CMOS technology without any penalty in throughput for any of the above modes.

Published in:

Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004. International Conference on  (Volume:2 )

Date of Conference:

5-7 April 2004