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A self-reconfigurable hardware architecture for mesh arrays using single/double vertical track switches

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2 Author(s)
M. Fukushi ; Graduate Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan ; S. Horiguchi

This paper deals with the issue of reconfiguring mesh-connected processor arrays (mesh arrays) in the presence of faulty processors. For massively parallel systems, it has become necessary to develop built-in self-reconfigurable systems that can automatically reconfigure partially faulty systems. Many reconfiguration methods have been proposed to date; however, most of them are not suitable for self-reconfiguration. In this paper, we propose a self-reconfiguration method based on simple column bypass and south directional rerouting schemes. This proposal offers the combined advantages of high probability of successful reconfiguration, low hardware overhead, and simplicity of implementation. A switching mechanism, which can determine the desired switch functions automatically using the states of neighboring processors, makes the implementation of our method easier. Simulated results show that the proposed method achieves a higher system yield than that of previous methods with half the number of redundant switches and interconnections. The prototype system of self-reconfigurable mesh arrays is implemented using a field-programmable gate array (FPGA) and the hardware overhead is discussed.

Published in:

IEEE Transactions on Instrumentation and Measurement  (Volume:53 ,  Issue: 2 )