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In this paper, we present a switched-capacitor sigma-delta (Σ-Δ) modulator for high resolution applications. In particular, this Σ-Δ modulator is well suited for distributed sensor networks. The circuit, implemented in a double-poly, double-metal 0.6 μm CMOS technology, is based on a fourth-order single-loop architecture with a sampling frequency of 256 kHz. The chip consumes 50 mW from a single 5-V supply and achieves a signal-to-noise ratio of 104.9 dB over a bandwidth of 400 Hz, corresponding to a resolution of 17.1 bits.
Instrumentation and Measurement, IEEE Transactions on (Volume:53 , Issue: 2 )
Date of Publication: April 2004