On the design of a self-reconfigurable SoPC cryptographic engine

We present a SoPC (system-on-a-programmable-chip) embedded system featuring self-reconfigurable capability. It addresses the factors that limit the system performance when FPGAs are used to implement various encryption algorithms dynamically. The limiting factors are the data transfer rate between the host and the FPGA, and the reconfiguration latency. The results generated by the cryptographic engine reported show that in order to attain optimal performance, it is crucial to floor-plan the reconfigurable part of the FPGA.