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The quasi-planar double-gate FinFET has emerged as one of the most likely successors to the classical planar MOSFET for ultimate scalability. Unlike planar devices, its channel width is in the vertical direction; hence it is possible to increase effective channel width (and hence drive current) per unit planar area by increasing fin-height (SOI thickness). This translates directly to improved performance in interconnect-dominated circuits. In this paper we explore the joint Vdd-fin-height-Vt design space for a 65 nm FinFET SRAM. We report that 69% taller fins can accommodate 18% (140 mV) lower Vdd as well as 35 % (70 mV) higher Vt to deliver iso-performance at 87% lower sub-threshold leakage, 50% lower gate leakage, 25% lower dynamic energy, 13% higher static noise margin and 38% higher critical charge for soft-error immunity.