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Continued scaling of silicon process technologies beyond the 90nm node will face problems due to within die process variations. The increasing relative magnitude of within die process variations will cause power-frequency distributions to widen, thus reducing manufacturing yields. Mitigating the effects of these process variations can be done by using a system of locally-generated body biases. This system allows for highly localized circuit optimizations with very little overhead in silicon area and routing resources. We present two algorithms to find near-optimal configurations of these biases which can be applied during post-fabrication testing. The system can improve an initial yield of 12% to 73%.