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Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levels

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3 Author(s)
Ming-Dou Ker ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Wei-Jen Chang ; Wen-Yu Lo

An ESD protection design for mixed-voltage I/O interfaces with low-voltage-triggered PNP (LVTPNP) devices is proposed in this paper. The LVTPNP, by inserting N+ or P+ diffusion across the junction between the N-well and P-substrate of the PNP devices, is designed to protect the mixed-voltage I/O pads for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS). The experimental results in a 0.35 μm CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device.

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Quality Electronic Design, 2004. Proceedings. 5th International Symposium on

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