By Topic

Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levels

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ming-Dou Ker ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Wei-Jen Chang ; Wen-Yu Lo

An ESD protection design for mixed-voltage I/O interfaces with low-voltage-triggered PNP (LVTPNP) devices is proposed in this paper. The LVTPNP, by inserting N+ or P+ diffusion across the junction between the N-well and P-substrate of the PNP devices, is designed to protect the mixed-voltage I/O pads for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS). The experimental results in a 0.35 μm CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device.

Published in:

Quality Electronic Design, 2004. Proceedings. 5th International Symposium on

Date of Conference:

2004