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In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role on determining circuit quality indicated by timing, power consumption, cost, power supply noise and tolerance to process variations. In this paper, a clock tree routing algorithm is proposed to achieve any prescribed non-zero skews which are useful in reducing clock cycle time, suppressing power supply noise and improving tolerance to process variations. The interactions among skew targets, sink location proximities and capacitive load balance are analyzed. Based on this analysis, a maximum delay-target ordering merging scheme is suggested to minimize wire and buffer area which imply cost, power consumption and vulnerability to process variations. During the clock routing, buffers are inserted simultaneously to facilitate a proper skew rate level and reduce wire snaking. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that the proposed algorithm can reduce the total wire and buffer capacitance by 60% over an extension of existing zero skew routing method.
Date of Conference: 2004