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Integrated circuits have to be robust to manufacturing variations. This paper presents a new statistical methodology to determine the worst-case corners for a set of circuit performances. Our methodology first estimates response surfaces for circuit performances as quadratic functions of the process parameters with known statistical distributions. These response surface models are then used to extract the worst-case corners in the process parameter space as the points where the circuit performances are at their min/max values corresponding to a specified statistical level. Corners in the process parameter space close to each other are clustered to reduce their number, which reduces the number of simulations required for design verification. We introduce the novel concept of relaxation coefficient to ensure that the corners capture the min/max values of all the circuit performances at the desired statistical level. The corners are realistic since they track the multivariate statistical distribution of the process parameters. Expected worst-case circuit performances can thus be extracted with a small number of simulations suitable for subsequent design verifications. The methodology is demonstrated with examples showing extraction of corners from digital standard cells and also the corners for analog/RF blocks found in typical communication ICs.