By Topic

A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18 μm CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Chen Xu ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China ; Chao Shen ; Bermak, A. ; Chan, M.

In this paper, a digital pixel architecture with pixel-level ADC based on Pulse Width Modulation (PWM) scheme and an 8-bit DRAM is proposed to operate at an extremely low voltage environment, i.e., 1.2 V. This digital pixel architecture is designed to eliminate the restriction of low supply voltage imposed by device scaling trend. The pixel is implemented in a commercially available 0.18 μm, single poly and 6 metal CMOS process. Simulation results show that the circuit is functional at a VDD of 1.2 V with a higher dynamic range and lower power consumption as compared to conventional CMOS APS architecture.

Published in:

Electron Devices and Solid-State Circuits, 2003 IEEE Conference on

Date of Conference:

16-18 Dec. 2003