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A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18 μm CMOS technology

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4 Author(s)
Chen Xu ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China ; Chao Shen ; Bermak, A. ; Chan, M.

In this paper, a digital pixel architecture with pixel-level ADC based on Pulse Width Modulation (PWM) scheme and an 8-bit DRAM is proposed to operate at an extremely low voltage environment, i.e., 1.2 V. This digital pixel architecture is designed to eliminate the restriction of low supply voltage imposed by device scaling trend. The pixel is implemented in a commercially available 0.18 μm, single poly and 6 metal CMOS process. Simulation results show that the circuit is functional at a VDD of 1.2 V with a higher dynamic range and lower power consumption as compared to conventional CMOS APS architecture.

Published in:

Electron Devices and Solid-State Circuits, 2003 IEEE Conference on

Date of Conference:

16-18 Dec. 2003

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