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A novel 0.8 V BP-DTMOS content addressable memory cell circuit derived from SOI-DTMOS techniques

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2 Author(s)
Shen, E. ; Waterloo Univ., Ont., Canada ; Kuo, J.B.

This paper reports a novel 0.8 V BP-DTMOS content addressable memory (CAM) cell circuit derived from SOI DTMOS techniques, implemented in a 0.18 μm bulk CMOS technology. According to experimentally measured results of a test chip, this 0.8 V CAM cell derived from SOI-DTMOS techniques has 1.7 ns tag-compare time, which is 47% faster as compared to the one without using the BP-DTMOS technique.

Published in:

Electron Devices and Solid-State Circuits, 2003 IEEE Conference on

Date of Conference:

16-18 Dec. 2003

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