A novel 0.8 V BP-DTMOS content addressable memory cell circuit derived from SOI-DTMOS techniques

This paper reports a novel 0.8 V BP-DTMOS content addressable memory (CAM) cell circuit derived from SOI DTMOS techniques, implemented in a 0.18 /spl mu/m bulk CMOS technology. According to experimentally measured results of a test chip, this 0.8 V CAM cell derived from SOI-DTMOS techniques has 1.7 ns tag-compare time, which is 47% faster as compared to the one without using the BP-DTMOS technique.