Referenced Items are not available for this document.
This paper presents a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets at reducing extra off-chip memory accesses caused by interprocessor communication. This is achieved by increasing the application-wide reuse of data that resides in scratch-pad memories of processors. Our results obtained using four array-intensive image processing applications indicate that exploiting interprocessor data sharing can reduce energy-delay product significantly on a four-processor embedded system.
Published in:
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
(Volume:12
,
Issue:
3
)
Date of Publication: March 2004
- Page(s):
- 281 - 287
- ISSN :
- 1063-8210
- INSPEC Accession Number:
- 7976869
- Digital Object Identifier :
- 10.1109/TVLSI.2004.824299
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 05 April 2004
- Issue Date :
- March 2004
- Sponsored by :
- IEEE Circuits and Systems Society
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