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Compiler-directed scratch pad memory optimization for embedded multiprocessors

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5 Author(s)
Kandemir, M. ; Pennsylvania State Univ., University Park, PA, USA ; Kadayif, I. ; Choudhary, A. ; Ramanujam, J.
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This paper presents a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets at reducing extra off-chip memory accesses caused by interprocessor communication. This is achieved by increasing the application-wide reuse of data that resides in scratch-pad memories of processors. Our results obtained using four array-intensive image processing applications indicate that exploiting interprocessor data sharing can reduce energy-delay product significantly on a four-processor embedded system.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:12 ,  Issue: 3 )