System Maintenance Notice:
Single article purchases and IEEE account management are currently unavailable. We apologize for the inconvenience.
By Topic

Development of a verification method for timed function blocks using ESDT and SMV

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
3 Author(s)
Myung Jun Song ; Dept. of Nucl. & Quantum Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea ; Seo Ryong Koo ; Poong Hyun Seong

As programmable logic controllers (PLCs) are widely used in the digital instrumentation and control (I&C) systems of nuclear power plants (NPPs), the safety of PLC software has become the most important consideration. In this work, we propose a method to perform effective verification activities on the traceability analysis and the software design evaluation in the software design phase. In order to perform the traceability analysis between software requirement specification (SRS) written in a natural language and software design specification (SDS) written in function block diagram (FBD), this method uses extended- structured decision table (ESDT). ESDTs include information related to the traceability analysis from SRS and SDS, respectively. Through comparing with two ESDTs, an effective traceability analysis can be achieved. For the software design evaluation, we use model checking as a formal verification method. FBD-style design specification is translated into symbolic model verifier (SMV) input language and then the FBD-style design specification can be formally analyzed using SMV model checker.

Published in:

High Assurance Systems Engineering, 2004. Proceedings. Eighth IEEE International Symposium on

Date of Conference:

25-26 March 2004