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Using dynamic binary translation to fuse dependent instructions

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2 Author(s)
Hu, S. ; Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA ; Smith, J.E.

Instruction scheduling hardware can be simplified and easily pipelined if pairs of dependent instructions are fused so they share a single instruction scheduling slot. We study an implementation of the x86 ISA that dynamically translates x86 code to an underlying ISA that supports instruction fusing. A microarchitecture that is codesigned with the fused instruction set completes the implementation. We focus on the dynamic binary translator for such a codesigned x86 virtual machine. The dynamic binary translator first cracks x86 instructions belonging to hot superblocks into RISC-style microoperations, and then uses heuristics to fuse together pairs of dependent microoperations. Experimental results with SPEC2000 integer benchmarks demonstrate that: (1) the fused ISA with dynamic binary translation reduces the number of scheduling decisions by about 30% versus a conventional implementation that uses hardware cracking into RISC microoperations; (2) an instruction scheduling slot needs only hold two source register fields even though it may hold two instructions; (3) translations generated in the proposed ISA consume about 30% less storage than a corresponding fixed-length RISC-style ISA.

Published in:

Code Generation and Optimization, 2004. CGO 2004. International Symposium on

Date of Conference:

20-24 March 2004

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