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Improving 64-bit Java IPF performance by compressing heap references

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8 Author(s)
Adl-Tabatabai, A.-R. ; Microprocessor Technol. Lab, Intel Corp., USA ; Jay Bharadwaj ; Cierniak, M. ; Eng, M.
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64-bit processor architectures like the Intel® Itanium® processor family are designed for large applications that need large memory addresses. When running applications that fit within a 32-bit address space, 64-bit CPUs are at a disadvantage compared to 32-bit CPUs because of the larger memory footprints for their data. This results in worse cache and TLB utilization, and consequently lower performance because of increased miss ratios. This paper considers software techniques for virtual machines that allow 32-bit pointers to be used on 64-bit CPUs for managed runtime applications that do not need the full 64-bit address space. We describe our pointer compression techniques and discuss our experience implementing these for Java applications. In addition, we give performance results with our techniques for both the SPEC JVM98 and SPEC JBB2000 benchmarks. We demonstrate a 12% performance improvement on SPEC JBB2000 and a reduction in the number of garbage collections required for a given heap size.

Published in:

Code Generation and Optimization, 2004. CGO 2004. International Symposium on

Date of Conference:

20-24 March 2004