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A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis

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3 Author(s)
Verma, S. ; Center for Integrated Syst., Stanford Univ., CA, USA ; Junfeng Xu ; Lee, T.H.

A frequency-synthesis technique which extracts the Nth harmonic from an N-stage oscillator is presented. This technique enables significant power savings in the prescaler of a frequency synthesizer. The maximum achievable voltage swing from such an oscillator is estimated. To study this technique, a multiply-by-3 circuit with two 180°-coupled single-ended three-stage ring oscillators has been fabricated in 0.24-μm CMOS, designed to work in the 902-928-MHz ISM band (U.S. and Canada). It provides two outputs: one at the normal operating frequency of the oscillator and the other at three times that frequency. The circuit can work at voltages as low as 1.3 V, while consuming 210 μA of current.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:39 ,  Issue: 4 )